This invention relates to electrical signal filters and particularly to programmable tapped delay line filters.
The wide range of electrical signals used in the fields of communication, navigation and signal identification demands highly flexible signal processing devices. Recently, particular emphasis has been placed upon the implementation of programmable filtering functions. Programmable filters greatly simplify the implementation of analog interfaces in complex signal processing systems. Many approaches have been taken to create near-ideal programmable filters. In general, each approach seeks to optimize the efficiency, cost, size, and performance of the filter.
A tapped delay line filter produces a frequency response by summing weighted, delayed versions of its input. Because the filter response is completely controlled by the tap weights, tapped delay line filters are highly programmable. Recent advances in process technology allow the integration of delay lines onto semiconducting substrates. Thus the full integration of programmable tapped delay line filters is feasible. This high level of integration allows tapped delay line filters to far surpass previous cost and size restrictions.
Many different methods for programming tapped delay line filters have been explored. In each method, an electrical control quantity is used to influence the electrical parameters of the delay line. The electrical parameters of the delay line then directly determine the weighting of the delay line taps. In some programmable delay line filters, the electrical reference quantities are continuous external inputs to the filter circuit. In other cases, the electrical control quantities are stored within the tap-weight control circuitry by an electrical storage apparatus.
One known programmable tapped delay line filter is shown in FIG. 1A. In FIG. 1A, the tap weights are determined by electrical parameters of the delay line. Specifically, the weights of the taps are determined by the capacitance between the tapping conductors 1 and substrate 2. This capacitance, indicated in the figure by C.sub.tap 3, is connected to an output bus 38 via an output capacitance C.sub.out 4 in such a way that the two capacitors form a capacitive current divider. The ratio of the current flowing in C.sub.tap 3 to the current flowing in C.sub.out 4 is directly determined by the respective capacitance ratio. The current ratio determines the effective tap weight. Thus the tap weight is indirectly controlled by the capacitance ratio. In the embodiment of FIG. 1, the capacitance C.sub.out 4 has a fixed value, but the value of the capacitance C.sub.tap 3 is a strong non-linear function of the DC bias voltage of the tap. This DC bias voltage is called V.sub.tap. Therefore, in this embodiment, the effective tap weight can be controlled by adjusting the DC bias voltage V.sub.tap . The DC bias voltage is controlled by the tap weight programming circuit illustrated on the right side of FIG. 1A. The outputs Q.sub.i on lines 5 of a shift register 6 connect to several FET switches 7. When the shift register 6 sets an output on a line 5 to a positive logic state, the corresponding FET switch 7 is closed, and the tap weight programming bus 8 is connected to the corresponding delay line tap 1. In this way, a voltage can be placed onto the tap capacitance C.sub.tap. The circuit of FIG. 1A has the disadvantage that the tap capacitance value C.sub.tap is very sensitive to defects in the physical geometry of the taps 1 and substrate 2. Thus the tap weights cannot be programmed accurately. In addition, because of the circuit design, the shift register 6 must have as many outputs as the number of taps in the delay line. This restriction can severely limit the density of the taps on the delay line.
FIG. 1B shows an alternative tap programming mechanism. Each shift register output on a line 5 is used to program two taps 1. When a shift register output 5 is set to a positive logic state, the corresponding master FET switch 9 is closed. Two additional signals .phi..sub.odd, .phi..sub.even 10 then close all switches 11 or all switches 11'. In this way, each of the taps 1 can be separately connected to the programming voltage on the programming bus 8. Through the use of the additional signals on lines 10, the circuit can use a shift register 6 which is half as long as the number of taps.
FIG. 2 shows a tap weighting apparatus based upon a dual gate field effect transistor (DGFET) 12 which cooperates with resistor R and supply voltage V.sub.DD to form a transistor amplifier. The gain of the transistor amplifier is controlled by the voltage V.sub.gain. The output of each DGFET amplifier is summed with the outputs of other amplifiers in a summation mechanism 13. This system is less sensitive to defects in the geometry of the substrate and taps because the weighting mechanism does not depend upon tap capacitance. However, because of its unusual structure, the dual gate FET 12 has not been manufactured on the same semiconducting substrate as the tapped delay line, So this implementation has not taken advantage of a single substrate architecture.
Another solution using dual gate FET's 12, a resistor R, and a supply voltage V.sub.DD to form an amplifier is shown in FIG. 3A and 3B. In FIG. 3B each delay line tap 1 is connected to an array of dual gate FET's 12. Each FET 12 in the array has a different geometry, and thus has a different output gain. The second gate of each FET 12 is controlled by a digital gain control voltage G.sub.1 -G.sub.4. As illustrated in FIG. 3A, a digital latch 14 connected to a digital tap weight programming bus 39 is used to store the state of the gain control voltage. The states of the gain control voltages are selected to produce the desired overall tap gain. This programming mechanism allows digital storage of tap weights, however, as in the circuit of FIG. 2, the use of DGFET's 12 has necessitated the use of two separate substrates. In addition, the digital latches 14 consume large amounts of area.
FIG. 4 shows an alternative tap weight programming mechanism, In FIG. 4, the tap weight is a function of the non-linear capacitance of the tap C.sub.tap 3, the output capacitance C.sub.out 4, and the incremental resistance of two diodes D1 and D2 designated at 19. The tap bias voltage V.sub.tap (and therefore the tap capacitance C.sub.tap) and the diode incremental resistances are controlled by the currents in two current sources S.sub.1, S.sub.2, designated at 20 (having a series resistance R). This tap weighting mechanism is effective, but it relies on tap capacitance, and thus is sensitive to defects in the substrate and tap geometries. In addition, a set of programming current sources 20 must be implemented for each tap, resulting in a large amount of control circuitry.
FIG. 5 shows another solution to tap weighting. The tap weight is controlled by a pair of field effect transistors 15 which cooperate with a supply voltage V.sub.DD to form an amplifier, The tap voltage drives the gate of one FET 15 and a gain voltage 21 drives the gate of the other FET 15. In this system, the same gain voltage 21 is supplied to each tap amplifier. Therefore, each tap has the same gain. After the tap amplifier, the amplifier tap voltage is connected to a positive or negative summing bus 17, 18 by two switching FET's 16 which are controlled by digital signal TO.sub.+ and TO.sub.-. In this way, the tap may have a +1 or -1 relative gain. The programming circuitry can be quite simple, because digital voltages are used to select the relative gain. However, the lack of continuous gain adjustment limits the circuit's programmability.